A mixed-mode fault simulator for VLSI MOS devices

With the progression from large scale integration (LSI) to very large scale integration (VLSI), and eventually ultra large scale integration (ULSI), integrated circuit fault coverage is becoming increasingly important. Naturally as we move from LSI towards ULSI the area consumed by devices is getting ever larger. Larger area devices are known to have a higher probability of containing manufacturing induced defects. Fault analysis attempts to measure how well a given set of tests can detect these manufacturing induced defects. One typical means of performing fault analysis is to compare the response of a known "good" (unfaulty) logical circuit, to some stimulus, with that of one containing a fault. However, it can be extremely costly and time consuming to obtain an accurate fault coverage analysis for a VLSI integrated circuit containing many thousands of gates. The cost and time of fault analysis can be contained with a unique technique • presented in this thesis. This technique is a serial fault simulation implementation, which uses both the C programming language and switch-Ieve1logic simulations, combined, to yield both a cost and time effective method for determining the fault coverage of an integrated circuit.